High Speed Digital Design: Design of High Speed Interconnects and Signaling

Hanqiao Zhang is an Analog Engineer at Intel and holds a PhD degree in Electromagnetics and Microwave Engineering from Clemson University. Hanqiao joined Intel Xeon product electrical validation team in 2011, where he made significant contributions to various high-speed digital system designs. He developed methodologies for validating next generation chip and high-speed interfaces for PCI Express and Quick Path Interface (QPI). Hanqiao transitioned into a signal integrity engineer with Intel Joint Innovation Center in DuPont WA in 2014. He now designs mission critical servers with Intel products. Hanqiao is a regular contributor to journals including IEEE Transactions, Journal of Applied Physics and Applied Physics Letters. Hanqiao has 10 years of experience on novel passive RF/microwave component design. Steve Krooswyk has been at Intel since 2003 when we joined as a signal integrity engineer for EPSD server development. In 2009, Steve transitioned into the signal integrity lead for PCI Express in Intel's Enterprise Platform Technology Division (EPTD). In addition to server products, his experience includes involvement in the PCI Express 3.0 and 4.0 specifications. He holds a B.S. and M.S. in electrical engineering from the University of South Carolina. Jeffrey Ou joined Intel in 1999 as an analog design engineer in CMOS RF transceiver design. In 2006, Jeffrey transitioned to Xeon processor product design team in Server Development Group (SDG) developing a serial I/O module configurable for PCI Express and Quick Path Interface (QPI). Since then Jeffrey has been involved in several generations of Xeon products from design to post silicon validation. In 2012, Jeffrey was recognized as a tech lead in SDG, and continued to develop the cutting-edge high speed serial I/O modules for server products. Jeffrey holds a PhD degree in EECS from UC Berkeley and is a member of IEEE.