Complete Symbolic Simulation of SystemC Models

In hismaster thesis, Vladimir Herdt presents a novel approach, called completesymbolic simulation, for a more efficient verification ofmuch larger (non-terminating) SystemC programs. Theapproach combines symbolic simulation with stateful model checking and allowsto verify safety properties in (cyclic) finite state spaces, by exhaustiveexploration of all possible inputs and process schedulings. The state explosionproblem is alleviated by integrating two complementary reduction techniques. Comparedto existing approaches, the complete symbolic simulation works more efficiently,and therefore can provide correctness proofs for larger systems, which is oneof the most challenging tasks, due to the ever increasing complexity.ContentsVerification of SystemsIntroduction toFormal Verification of SystemC ModelsSymbolic ModelChecking with Partial Order ReductionEfficient SymbolicState Matching using State SubsumptionHeuristic Approachesfor Symbolic State MatchingEvaluation ofProposed Techniques TargetGroupsLecturers and Studentsof Computer Sciences and Electrical EngineeringHardware Designersand Verification Engineers using SystemCTheAuthorVladimir Herdt is working as ResearchAssistant in the Group of Computer Architecture at the University of Bremen,where he is pursuing his PhD degree.