Nanometer Technology Designs

While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip defects. For nanometer technology designs, the traditional test methods cannot ensure a high quality level of chips, and at-speed tests using path and transition delay fault model have become a requirement in technologies below 180nm.Nanometer Technology Designs: High-Quality Delay Tests discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the delay test for nanotechnology designs. Topics covered include:At-speed test challenges for nanotechnologyLow-cost tester-friendly design-for-test techniquesImproving test quality of current at-speed test methodsFunctionally un-testable fault list generation and avoidanceTiming-based ATPG for screening small delay faultsFaster-than-at-speed test considering power supply noisePower supply noise tolerant at-speed test pattern generation and applicationSolutions for dealing with crosstalk and signal integrity issuesNanometer Technology Designs: High-Quality Delay Tests is a reference for practicing engineers and researchers in both industry and academia who are interested in learning about and implementing the most-advanced methods in nanometer delay testing.