High-Level Synthesis: From Algorithm to Digital Circuit
The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the spec…
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Produktdetails
Weitere Autoren: Morawiec, Adam (Hrsg.)
- ISBN: 978-1-4020-8587-1
- EAN: 9781402085871
- Produktnummer: 3745214
- Verlag: Springer Nature
- Sprache: Englisch
- Erscheinungsjahr: 2008
- Seitenangabe: 297 S.
- Masse: H24.3 cm x B16.2 cm x D2.4 cm 613 g
- Auflage: 2008
- Gewicht: 613
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