A Pipelined Multi-core MIPS Machine
Hardware Implementation and Correctness Proof
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.Constructions are in a gate level hardware model and thus deterministic…
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Produktdetails
Weitere Autoren: Müller, Silvia M. / Paul, Wolfgang J.
- ISBN: 978-3-319-13906-7
- EAN: 9783319139067
- Produktnummer: 33301317
- Verlag: Springer-Verlag GmbH
- Sprache: Englisch
- Erscheinungsjahr: 2014
- Seitenangabe: 352 S.
- Plattform: PDF
- Masse: 5'693 KB
- Auflage: 2014
- Abbildungen: 147 schwarz-weiße Abbildungen, Bibliographie
- Reihenbandnummer: 9000
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