Manufacturability Aware Routing in Nanometer VLSI

Nanometer very large scale integrated (VLSI) circuit design faces tremendous challenges due to the manufacturing limitations. These manufacturing and process related challenges include the printability issues due to deep sub-wavelength lithography, the topography variations due to chemical-mechanical polishing (CMP), the random defects due to missing or extra material, and so on. Thus, design closure may not automatically guarantee the manufacturing closure due to the manufacturing yield loss. Manufacturability aware layout optimization plays a key role in the overall yield improvement. Manufacturability Aware Routing in Nanometer VLSI examines key aspects of manufacturability issues and how to alleviate them during the routing stage. It shows that various key manufacturability issues can be optimized at different routing stages according to the granularity of routing algorithms and the availability of inputs to models. It surveys both model-based manufacturability optimization and rule-based yield improvement during routing. Existing industry design for manufacturability (DFM) practices mainly rely on either rule-based optimization or post-layout enhancement guided by modeling. Manufacturability Aware Routing in Nanometer VLSI demonstrates that there are tremendous opportunities to capture the downstream manufacturing/process effects, and abstract them early into the key physical design stage, through model-based manufacturability aware routing optimization.