Formal Semantics for VHDL
It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic. If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descript…
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Produktdetails
Weitere Autoren: Delgado Kloos, Carlos (Hrsg.)
- ISBN: 978-1-4613-5941-8
- EAN: 9781461359418
- Produktnummer: 15409857
- Verlag: Springer Us
- Sprache: Englisch
- Erscheinungsjahr: 2012
- Seitenangabe: 268 S.
- Masse: H24.0 cm x B16.0 cm x D1.4 cm 434 g
- Auflage: Softcover reprint of the original 1st ed. 1995
- Abbildungen: Paperback
- Gewicht: 434
2 weitere Werke von P. (Hrsg.) Breuer:
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