Abhishek Jain

Universal Verification Methodology Based Verification Environment

Theory and Practice

Buch

Ever increasing silicon design complexity and transistor density, product differentiation and time to market are major factors creating huge pressure on complete design flow. This book covers Verification phase by describing the concepts of Universal Verification Methodology (UVM) and by presenting a pragmatic approach of developing efficient and unified advanced verification environment at all levels using Universal Verification Methodology along with Assertion based verification, hardware acceleration and Transaction Level Modeling. This book is written primarily for verification engineers performing verification of complex IP blocks or ent… Mehr

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Produktdetails

ISBN: 978-3-659-47604-4
EAN: 9783659476044
Produktnummer: 37717443
Verlag: LAP Lambert Academic Publishing
Sprache: Englisch
Erscheinungsjahr: 2014
Seitenangabe: 140 S.
Masse: H22.0 cm x B15.0 cm x D0.8 cm 227 g
Abbildungen: Paperback
Gewicht: 227

Über den Autor

Abhishek Jain, Technical Manager at STMicroelectronics, India, has done M.Tech in Computer Science from IETE, M.Sc. Electronics from University of Delhi and PGDBA in Operations Management from Symbiosis. Driving key activities on Functional Verification Flow in Imaging group of STMicroelectronics.Doing Research in Efficient Verification Management.