Timing and Signal Integrity Issues with VLSI Interconnects
In sub-nanometer designs
This book discusses the timing and signal integrity issues with VLSI interconnects in sub-nanometer designs. Starting with the basics of interconnect equivalent circuit model it describes the RLC equivalent models of interconnects, their extraction methodologies, and circuit simulation for timing and signal integrity analysis. With enormous analysis results for different technology nodes the importance of on-chip inductive effects has been discussed. The sample simulation model along with the SPICE netlist for timing and signal integrity analysis has been provided in the appendix. The book will be useful to the teachers, students, and…
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Produktdetails
- ISBN: 978-3-8465-5243-8
- EAN: 9783846552438
- Produktnummer: 37800534
- Verlag: LAP Lambert Academic Publishing
- Sprache: Englisch
- Erscheinungsjahr: 2011
- Seitenangabe: 84 S.
- Masse: H22.0 cm x B15.0 cm x D0.5 cm 143 g
- Abbildungen: Paperback
- Gewicht: 143
Über den Autor
Debaprasad Das is Assistant Professor, Department of Electronics and Communication Engineering, Meghnad Saha Institute of Technology, Kolkata, India. He was a Senior Engineer at the ASIC product development centre, Texas Instruments, Bangalore, India. He has published many national and international papers in various conferences and journals.
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