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Brian (Hrsg.) Bailey

Taxonomies for the Development and Verification of Digital Systems

Buch

In the complicated world of system-on-chip design, we need a common language so we know what we're talking about.  By providing definitions for the terms used in the modeling, implementation, and verification of electronic systems, the taxonomies described in this book will help us find a common understanding. --Richard Goering, Group Editorial Director for Design Automation, Electronic Engineering TimesSuccessful industries must have a firm foundation for the vaocabulary that they use to communicate ideas and to avoid misunderstandings.  VSIA tackled this problem by developing a series of related taxonomies.  This book includes all this mate… Mehr

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Produktdetails


Weitere Autoren: Martin, Grant (Hrsg.) / Anderson, Thomas (Hrsg.)
  • ISBN: 978-1-4419-3681-3
  • EAN: 9781441936813
  • Produktnummer: 10301320
  • Verlag: Springer Nature EN
  • Sprache: Englisch
  • Erscheinungsjahr: 2010
  • Seitenangabe: 180 S.
  • Masse: H23.5 cm x B15.5 cm 314 g
  • Auflage: Softcover reprint of hardcover 1st ed. 2005
  • Gewicht: 314

Über den Autor


Brian Bailey is an independent functional verification consultant helping system designers improve their verification efficiency, and providing guidance and technology services to small start-up companies. He has spent over 20 years creating verification solutions in a number of EDA companies and in recent years has spent most of his time helping the industry understand how and when to adopt new verification methodologies.Grant Martin is a chief scientist at Tensilica, Inc. in Santa Clara, CA. Prior to Tensilica, Grant worked at Burroughs in Scotland for 6 years, BNR/Nortel in Canada for 10 years, and Cadence for 9 years. His main areas of interest are IP-based design, platform-based design of SoC, and system-level design.Thomas Anderson is a Director of Technical Marketing at Synopsys, Inc. in Mountain View, CA and chair of the VSIA functional verification working group. Previously he was Vice President of Applications Engineering at 0-In and Vice President of Engineering at Virtual Chips. He has authored over 100 papers and technical articles on verification, IP and interface standards.

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