Study and Analysis of Vedic Multipler and 16 Bit Arithmatic Unit
This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multipli…
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Produktdetails
Weitere Autoren: Kumar, Ram / Gupta, Radhe Shyam
- ISBN: 978-3-659-61392-0
- EAN: 9783659613920
- Produktnummer: 37430893
- Verlag: LAP Lambert Academic Publishing
- Sprache: Englisch
- Erscheinungsjahr: 2014
- Seitenangabe: 92 S.
- Masse: H22.0 cm x B15.0 cm x D0.6 cm 155 g
- Abbildungen: Paperback
- Gewicht: 155
Über den Autor
Dr K.L.Baishnab obtained his BE from (Regional Enginnering College Silchar) (presently National Institute of Technology Silchar INDIA) in the year 1995. M.Tech from Indian Institute of Technology kharagpur (INDIA) in the year 2004. PhD from NIT Silchar 2013.He is currently working as a Asst professor in ECE dept NIT Silchar (INDIA).
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