Impact of Spacer Engineering on Performance of Junctionless Transistor
The scaling of traditional planar CMOS devices is becoming difficult due to increasing gate leakage and subthreshold leakage. Multigate FETs have been proposed to overcome the limitations associated with the scaling of traditional CMOS devices below 100nm region. The multiple electrically coupled gates and the thin silicon body suppress the short-channel effects, thereby lowering the subthreshold leakage current in a multi-gate MOSFET. However, fabrication complexity increases for inversion mode (IM) FinFET devices due to ultra-steep doping profiles requirement. Junctionless transistor (JLT) overcomes the limitations associated with the creat…
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Produktdetails
Weitere Autoren: Gill, Sandeep Singh / Kaur, Navneet
- ISBN: 978-613-9-45556-0
- EAN: 9786139455560
- Produktnummer: 37353587
- Verlag: LAP Lambert Academic Publishing
- Sprache: Englisch
- Erscheinungsjahr: 2019
- Seitenangabe: 88 S.
- Masse: H22.0 cm x B15.0 cm x D0.5 cm 149 g
- Abbildungen: Paperback
- Gewicht: 149
Über den Autor
Prabhjot Kaur received her B.tech in Electronics and communication engineering From Guru Nanak Dev Engineering College, Ludhiana in 2016. From the same college, She received M.tech degree in 2018. Her major research area is VLSI design.
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