Full-Chip Nanometer Routing Techniques
As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attribu…
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Produktdetails
Weitere Autoren: Chang, Yao-Wen / Chen, Sao-Jie
- ISBN: 978-1-4020-6194-3
- EAN: 9781402061943
- Produktnummer: 2900783
- Verlag: Springer Nature EN
- Sprache: Englisch
- Erscheinungsjahr: 2007
- Seitenangabe: 102 S.
- Masse: 1 Ex.; H23.5 cm x B15.5 cm 780 g
- Abbildungen: Book
- Gewicht: 780
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