Digital Design of SDRAM on Verilog
To design an 8 MB x 16 x 4-BAnk synchronous random access dynamic memory (SDRAM) (512 MB) using Verilog hardware description language, which can be used in any memory-based application. Today, computers, as well as other electronic systems that require large amounts of memory, use DRAMs for core memory. Due to the unique transistor cell structure of the DRAM, extremely dense memory networks can be constructed in a single device occupying a relatively small footprint. The conventional DRAM is controlled in an asynchronous manner, requiring the system designer to manually insert the standby states to meet the device specifications. Synchronizat…
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Produktdetails
Weitere Autoren: Singh, Ritesh
- ISBN: 978-620-4-72767-7
- EAN: 9786204727677
- Produktnummer: 38138072
- Verlag: LAP Lambert Academic Publishing
- Sprache: Englisch
- Erscheinungsjahr: 2021
- Seitenangabe: 60 S.
- Masse: H22.0 cm x B15.0 cm x D0.4 cm 107 g
- Abbildungen: Paperback
- Gewicht: 107
Über den Autor
Abhishek Kumar and Ritesh Singh, Assistant Professor, Department of Electrical Engineering, Manipal University Jaipur, Jaipur, India. Their area of research includes, Degital System Design, Modelling and Simulation, Flight Dynamics & Stability, UAV, and Nonlinear Control System, Model Based Design, Hypersonic Vehicles, Autonomous Systems.
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