Design of DPLL using CMOS Technology
PLLs work by continuously adjusting a voltage or current-driven oscillator to match (lock onto) the phase and frequency of an input signal. A circuit called a phase comparator causes the VCO to seek and lock onto the desired frequency, which is set via a Voltage Controlled Oscillator. When the VCO frequency differs from the reference frequency, the phase comparator produces an error voltage. Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This book introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind…
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Produktdetails
Weitere Autoren: Deshmukh, Ankita
- ISBN: 978-613-4-97815-6
- EAN: 9786134978156
- Produktnummer: 37486053
- Verlag: LAP Lambert Academic Publishing
- Sprache: Englisch
- Erscheinungsjahr: 2018
- Seitenangabe: 72 S.
- Masse: H22.0 cm x B15.0 cm x D0.4 cm 125 g
- Abbildungen: Paperback
- Gewicht: 125
Über den Autor
Mr. Shankar N. Dandare( M.Sc., M.E., Ph. D. ) is working as a Professor in Electronics Engineering Department, Babasaheb Naik College of Engineering, Pusad, India. He is a member of many professional bodies like ISTE, AMIE, and IETE. He has teaching experience of 34 years in Engineering UG and PG level and Main author of three engineering Books.
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