A Pipelined Multi-core MIPS Machine
Hardware Implementation and Correctness Proof
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.Constructions are in a gate level hardware model and thus deterministic…
Mehr
CHF 93.00
Preise inkl. MwSt. und Versandkosten (Portofrei ab CHF 40.00)
V105:
Folgt in ca. 15 Arbeitstagen
Produktdetails
Weitere Autoren: Paul, Wolfgang J. / Müller, Silvia M.
- ISBN: 978-3-319-13905-0
- EAN: 9783319139050
- Produktnummer: 17245861
- Verlag: Springer International Publishing
- Sprache: Englisch
- Erscheinungsjahr: 2014
- Seitenangabe: 364 S.
- Masse: H23.5 cm x B15.5 cm x D1.9 cm 552 g
- Auflage: 2014
- Abbildungen: Paperback
- Gewicht: 552
1 weiteres Werk von Mikhail Kovalev:
A Pipelined Multi-core MIPS Machine
Hardware Implementation and Correctness Proof
Hardware Implementation and Correctness Proof
Ebook (PDF Format)
CHF 77.00
Bewertungen
Anmelden