Michael Opoku Agyeman

3D Networks-on-Chip Architecture Optimization for Low Power Design

Buch

Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, nove… Mehr

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Produktdetails

ISBN: 978-3-659-75813-3
EAN: 9783659758133
Produktnummer: 37437843
Verlag: LAP Lambert Academic Publishing
Sprache: Englisch
Erscheinungsjahr: 2015
Seitenangabe: 180 S.
Masse: H22.0 cm x B15.0 cm x D1.1 cm 286 g
Abbildungen: Paperback
Gewicht: 286

Über den Autor

Dr Michael Opoku Agyeman received the BSc. (Hons.) in electrical and electronics engineering from KNUST, Ghana, in 2008, and the MSc. degree in embedded and distributed systems from LSBU, London, in 2009. He received the PhD from the department of computing at Glasgow Caledonian University, Glasgow, in 2014.